1. Field of the Invention
The present invention relates generally to plasma etch methods for forming patterned layers within microelectronics fabrications. More particularly, the present invention relates to plasma etch methods for forming patterned silicon containing dielectric layers within microelectronics fabrications.
2. Description of the Related Art
As microelectronics integration levels have increased and microelectronics device and conductor element dimensions have decreased, it has become increasingly important to form within advanced microelectronics fabrications narrow aperture width contact and interconnection vias through dielectric layers to access within those advanced microelectronics fabrications narrow linewidth patterned conductor layers and narrow linewidth microelectronics devices formed within those advanced microelectronics fabrications.
While narrow aperture width contact and interconnection vias of substantial areal density are invariably required within advanced microelectronics fabrications to fulfill advanced microelectronics integration requirements, narrow aperture width contact and interconnection vias of substantial areal density are typically not readily formed without problems within advanced microelectronics fabrications. In general, problems are typically encountered when it is desired to form through plasma etch methods within advanced microelectronics fabrications narrow aperture width contact and interconnection vias of aperture width and/or spacing of less than about 0.35 microns through dielectric layers of thicknesses greater than about 10000 angstroms. Under such conditions, narrow aperture width contact and interconnection vias of substantial areal density within advanced microelectronics fabrications are generally difficult to form due to: (1) a limited depth of focus through which may be formed patterned photoresist etch mask layers to be employed in forming high areal density narrow aperture width contact and interconnection vias within microelectronics fabrications; and (2) a typically comparatively low dielectric layer to photoresist etch mask layer plasma etch rate ratio of from about 2:1 to about 3:1 which in conjunction with the limited depth of focus provides inadequate photoresist etch mask layer thickness to adequately etch a narrow aperture width contact or interconnection via completely through a typical dielectric layer within an advanced microelectronics fabrication without completely consuming the patterned photoresist etch mask layer and thus consequently subsequently partially consuming the dielectric layer.
In order to avoid photoresist etch mask layer thickness limitations and consequent dielectric layer etch depth limitations within advanced microelectronics fabrications, it has been proposed in the art of advanced microelectronics fabrication to employ hard mask layers in place of photoresist etch mask layers when forming narrow aperture width contact and interconnection vias through dielectric layers, such as but not limited to silicon oxide dielectric layers, silicon nitride dielectric layers and silicon oxynitride dielectric layers, within advanced microelectronics fabrications through plasma etch methods. Although hard mask layers theoretically provide significant improvements in dielectric layer to hard mask layer etch selectivity within plasma etch methods within advanced microelectronics fabrications, such hard mask layers typically provide such improvements at the expense of: (1) dielectric layer plasma etch rate and/or; (2) contact or interconnection via sidewall etch profile.
It is thus desirable within the art of advanced microelectronics fabrication to provide hard masking methods and materials within plasma etch methods through which there may be formed comparatively narrow aperture width contact and interconnection vias through silicon containing dielectric layers within advanced microelectronics fabrications with improved (ie: increased) etch rates and improved (ie: smoother) via sidewall profiles. It is towards these goals that the present invention is generally directed.
Various novel plasma etch methods have been disclosed in the art of microelectronics fabrication to address various problems encountered when plasma etching microelectronics layers within microelectronics fabrications. For example, Tam et al., in U.S. Pat. No. 4,613,400, discloses a plasma hardening method for forming a patterned photoresist etch mask layer employed in forming a patterned chlorine containing plasma etchable layer with replicable dimensions within an integrated circuit microelectronics fabrication. The method provides for forming a silicon and chlorine containing barrier material layer upon the patterned photoresist layer and subsequently oxidizing the silicon and chlorine containing barrier material layer within an oxygen containing plasma.
In addition, Yanagida, in U.S. Pat. No. 5,338,399, discloses a plasma etch method for forming a contact via through a silicon containing dielectric layer within an integrated circuit microelectronics fabrication, where the contact via is formed with a high etch rate of the silicon containing dielectric layer, a high selectivity for the silicon containing dielectric layer with respect to a photoresist etch mask layer employed in defining the contact via, low particulate contamination of the silicon containing dielectric layer and low silicon semiconductor substrate damage. The plasma etch method employs when forming the contact via a cyclic saturated perfluorocarbon etchant gas or a cyclic unsaturated perfluorocarbon etchant gas which yields more perfluorocarbon radicals per molecule than a conventional carbon tetrafluoride etchant gas.
Finally, Kadomura, in U.S. Pat. No. 5,342,481 discloses a plasma etch method for anisotropic etching of blanket layers within microelectronics fabrications while employing reverse tapered patterned photoresist layers as photoresist etch mask layers when anisotropic etching the blanket layers within the microelectronics fabrications. The method employs a plasma which deposits discharge reaction products upon the reverse tapered patterned photoresist etch mask layer to provide a substantially vertically tapered patterned photoresist etch mask layer sidewall therefrom either prior to or concurrent with anisotropic etching a blanket layer to form a patterned layer therefrom with reproducible dimensions.
Desirable in the art are additional hard masking methods and materials within plasma etch methods through which there may be formed comparatively narrow aperture width contact and interconnection vias through dielectric layers within advanced microelectronics fabrications with improved etch rates and improved via sidewall profiles. More particularly desirable in the art are additional hard masking methods and materials within plasma etch methods through which there may be formed comparatively narrow aperture width contact and interconnection vias through dielectric layers within advanced integrated circuit microelectronics fabrications with improved etch rates and improved via sidewall profiles. It is towards these goals that the present invention is more specifically directed.